1. Field of the Invention
The present invention pertains to a semiconductor device and a method for manufacturing the same, and more particularly to the improvement in the resistance to hot carriers and variation of characteristics due to slow-trapping in MOS-type semiconductor devices.
2. Related Art
FIG. 5 depicts an example of a conventional MOS-type semiconductor device, which comprises a semiconductor substrate 101 having isolation regions 102 formed thereon, a well region 103 formed at the areas other than the isolation regions 102, source and drain regions 107 formed in the vicinity of the substrate surface, a gate oxide 104 disposed above these regions, and a gate electrode 105 of polysilicon formed on the gate oxide 104. Formed at the lateral sides of the gate electrode 105 are first oxide films 106 defining side walls for the gate electrode 105, and a second oxide film 108 is formed as an interlayer dielectric film covering the entire surface, while a BPSG (boron-phosphorous silicate glass) layer 110 is further provided thereon. Furthermore, the second oxide film 108 and the BPSG layer 110 selectively have contact openings 111 in which a barrier metal 112 and tungsten 113 are embedded. Moreover, first layer wirings 114 each formed of an aluminum-including alloy are present at the regions which include at least the areas above the contact openings 111. An interlayer dielectric film 115 formed of SiOF is formed on the first layer wirings 114, and a via hole 116 is selectively opened therethrough. Formed at the side walls of the via hole 116 are titanium nitride films 117 extending from a second layer wiring 119, and tungsten 118 is embedded therein. Moreover, second layer wirings 119 are formed at the areas including a portion above the via hole 116, and a cover film 120 formed of a plasma SiON is present thereon.
The method for manufacturing this semiconductor device will now be described with reference to FIGS. 6(a) and 6(b).
First, as shown in FIG. 6(a), isolation regions 102 are formed on the semiconductor substrate 101 by means of a selective oxidation process, and a well region 103 is then formed by means of a conventional ion-implantation process. Thereafter, the surface of the semiconductor substrate 101 is subjected to oxidation to form a gate oxide 104, and after polysilicon is formed thereon, these are formed into a desired pattern to produce a gate electrode 105. Subsequently, an oxide film is caused to grow over the entire surface, and is subjected to an anisotropic etch-back working to leave a first oxide film 106 only at the lateral sides of the gate electrode 105. Then, source and drain regions 107 are formed by means of ion implantation and activation thermal annealing, and a second oxide film 108 is formed over the entire surface thereof so as to have a film thickness of about 100 nm.
Subsequently, as shown in FIG. 6(b), BPSG 110 is formed by means of an atmospheric CVD process so as to have a film thickness of around 1200 .mu.m, and a surface thereof is polished by means of a CMP (chemical mechanical polishing) method to be flattened. Subsequently, after forming contact openings 111 selectively, a barrier metal 112 is provided, and the inside of each contact opening 111 is embedded with tungsten 113 deposited by CVD process, following which a first layer wiring 114 of an aluminum-containing alloy having a thickness of 0.4 .mu.m is formed and subjected to patterning. Thereafter, an interlayer dielectric film of SiOF is formed by means of a bias ECR (electron cyclotron resonance) plasma CVD process so as to have a film thickness of 0.8 .mu.m on the wiring. Further, a via hole 116 is selectively opened, and titanium nitride film 117 is deposited by a spattering method only with a small film thickness such as 50 nm, and tungsten 118 is deposited in the via hole 116 by a blanket CVD process, embedding the inside of the via hole 116 by effecting an etch-back working. Thereafter, a second layer wiring 119 is formed to effect a patterning, and a cover film 120 of SiON is finally deposited by means of a plasma CVD process so as to have a film thickness of about 1 .mu.m.
In the semiconductor device of the aforesaid structure, however, BPSG is employed in order to ensure the flatness of the interlayer dielectric film, and a film, such as SiON, which is susceptible to the inclusion of water is used in order to reduce wiring volume. Therefore, there are problems of reliability, such as relatively poor resistance to hot carriers and variation of characteristics due to slow-trapping. Furthermore, the poor resistance to hot carriers and variation of characteristics due to slow-trapping will be more significant when dielectric films such as coated films having a further reduced dielectric constant are selected as the interlayer dielectric films in order to reduce the wiring time loss to obtain higher speed for circuit. This is because such an interlayer dielectric film is more susceptible to the inclusion of water.
In order to avoid such lowering of the reliability in MOS transistors, a technique which involves imparting resistance to the formation of surface level by incorporation of nitrogen in the gate oxide has been proposed. Referring to FIG. 7, the technique described in Japanese Patent Application, First Publication No. Hei 5-283679, will be explained for the purpose of illustration. This technique is similar to that described above in that isolation regions 202, a well region 203 and a gate electrode 205 are formed in or on a semiconductor substrate 201, and in that first oxide films 206 serving as side walls, source and drain regions 207 and a second oxide film 208 are formed. However, the gate oxide film 221 has a two-layered structure consisting of a nitride oxide film 222 containing no less than 10.sup.19 cm.sup.-3 of nitrogen atoms and constituting an interface with the channel regions and a silicon oxide film 223 containing nitrogen atoms in a concentration of no greater than 10.sup.19 cm.sup.-3 and disposed on the nitride oxide film 222. With this construction, the nitride oxide film 222 of higher nitrogen concentration provided at the interface of the low concentration region exhibits a high resistance to the formation of surface level due to drain-avalanche-hot carrier implantation, whereas the silicon oxide film 223 of a lower nitrogen concentration lowers the average concentration of the entire dielectric film, reduces the fixed charge, and reduces oxide film-trapping, so that electric field modulation at the low concentration regions can be prevented.
Furthermore, another conventional technique, proposed in Japanese Patent Application, First Publication No. Hei 7-176743 and shown in FIG. 8, is also similar in that isolation regions 302, a well region 303 and a gate oxide 304 are formed in or on a semiconductor substrate 301, and in that first oxide films 306 serving as side walls, source and drain regions 307 and a second oxide film 308 are formed. However, the gate oxide film 304 is doped with nitrogen, and includes, as the gate electrode, a region 321 which is doped with nitrogen and a region 322 which is not doped with nitrogen. Therefore, the resistance to hot carriers can be improved. In addition, it is possible to prevent impurities within the source and drain regions 307 from diffusing longitudinally and transversely by doping nitrogen within the source and drain regions 307.
Thus, with the conventional techniques described in these publications, it is possible to impart the resistance to the formation of surface level by incorporating nitrogen in the gate oxide and gate electrode. However, nitrogen leaves outwardly by diffusion from the gate oxide and the gate electrode during a thermal process mainly at a wiring process. As a result, the advantages expected by the incorporation of nitrogen reduce or even diminish, and a sufficient performance regarding the resistance to hot carriers and variation of characteristics due to slow-trapping cannot be obtained.